Alif Semiconductor /AE302F80F55D5AE_CM55_HE_View /OSPI0 /OSPI_SPI_CTRLR0

Address and Instruction Transfer format. Selects whether OSPI will transmit instruction/address either in Standard SPI mode or the SPI mode selected in the OSPI_CTRLR0[SPI_FRF] bit field.

0 (Val_0x0): Instruction and Address will be sent in Standard SPI Mode.

1 (Val_0x1): Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by the OSPI_CTRLR0[SPI_FRF] bit field.

2 (Val_0x2): Both Instruction and Address will be sent in the mode specified by OSPI_CTRLR0[SPI_FRF] bit field.

This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the FIFO the transfer can begin. Note: For enhanced SPI modes, INST_L and ADDR_L cannot be both programmed to 0x0 at the same time.

0 (Val_0x0): No address

1 (Val_0x1): 4-bit address length

2 (Val_0x2): 8-bit address length

3 (Val_0x3): 12-bit address length

4 (Val_0x4): 16-bit address length

5 (Val_0x5): 20-bit address length

6 (Val_0x6): 24-bit address length

7 (Val_0x7): 28-bit address length

8 (Val_0x8): 32-bit address length

9 (Val_0x9): 36-bit address length

10 (Val_0xA): 40-bit address length

11 (Val_0xB): 44-bit address length

12 (Val_0xC): 48-bit address length

13 (Val_0xD): 52-bit address length

14 (Val_0xE): 56-bit address length

15 (Val_0xF): 60-bit address length

Mode bits enable in XIP mode. If this bit is set to 0x1, then in XIP mode of operation OSPI inserts Mode bits after the address phase. These bits are set in register OSPI_XIP_MODE_BITS register. The length of Mode bits defaults to 8-bits.

Dual/Quad/Octal mode instruction length in bits. Note: For enhanced SPI modes, INST_L and ADDR_L cannot be both programmed to 0x0 at the same time.

0 (Val_0x0): No Instruction.

1 (Val_0x1): 4-bit instruction length.

2 (Val_0x2): 8-bit instruction length.

3 (Val_0x3): 16-bit instruction length.

Wait cycles in Dual/Quad/Octal mode between control frames transmission and data reception. Specified as number of SPI clock cycles.

SPI DDR Enable bit. This bit enables Dual Data-Rate transfers in Dual/Quad/Octal frame formats of SPI.

Instruction DDR Enable bit. This bit enables Dual Data-Rate transfer for instruction phase.

Read Data Strobe Enable bit. Once this bit is set to 1 OSPI uses Read data strobe (RXDS) to capture read data in DDR mode.

Fix DFS for XIP transfers. If this bit is set to 1 then data frame size for XIP transfers is fixed to the programmed value in OSPI_CTRLR0[DFS] bit field. The number of data frames to fetch is determined by transfer size and burst type signals. If this bit is set to 0 then data frame size and number of data frames to fetch are both determined by transfer size and burst type signals.

XIP Instruction Enable bit. If this bit is set to 1 then XIP transfers also have an instruction phase. The instruction opcodes can be chosen from OSPI_XIP_INCR_INST or OSPI_XIP_WRAP_INST registers bases on AHB transfer type.

Enable Continuous Transfer in XIP mode. If this bit is set to 1 then continuous transfer mode in XIP is enabled, in this mode OSPI keeps the slave selected until a non-XIP transfer is detected on the AHB interface.

SPI Data Mask Enable bit. When this bit is enabled, the TXD_DM signal is used to mask the data on the TXD data line.

Enable RXDS Signaling during address and command phase of HyperBus transfer. This bit enables RXDS signaling by HyperBus slave devices during Command-Address (CA) phase. If the RXDS signal is set to 1 during the CA phase of transfer, OSPI transmits [2 x OSPI_SPI_CTRLR0[WAIT_CYCLES]) - 1] wait cycles after the address phase is complete.

XIP Mode Bits Length. Sets the length of Mode bits in XIP mode of operation. These bits are valid only when OSPI_SPI_CTRLR0[XIP_MD_BIT_EN] is set to 1.

0 (Val_0x0): Mode bits length equal to 2.

1 (Val_0x1): Mode bits length equal to 4.

2 (Val_0x2): Mode bits length equal to 8.

3 (Val_0x3): Mode bits length equal to 16.

Enables XIP Pre-fetch functionality in OSPI. Once enabled OSPI will pre-fetch data frames from next contiguous location, to reduce the latency for the upcoming contiguous transfer. If the next XIP request is not contiguous then pre-fetched bits will be discarded.